Macroscalar processor architecture
US8412914B2 · kind B2 · utility
44Cited by
42References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 17, 2011 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Nov 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for aggregating a program loop in a Macroscalar architecture includes identifying one or more instructions of the program loop having a branch instruction that causes the program loop to branch dependent upon a predicate condition after a memory write operation. The method also includes modifying at least one of the one or more instructions to cause a processor executing the one or more instructions to branch after the memory write operation executed as a vector block for iterations prior to and including an iteration during which the predicate condition is satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.