Global synchronization of parallel processors using clock pulse width modulation
US8412974B2 · kind B2 · utility
1Cited by
13References
21Claims
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Key dates
| Filing date | Jan 29, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Jun 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.