Vertically pinched junction field effect transistor
US8415720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2011 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Nov 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/832
Abstract
A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.