Power-on reset circuit and method
US8415993B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2011 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Oct 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.