Systems and methods of improved power amplifier efficiency through adjustments in crest factor reduction
US8416893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2010 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Mar 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/3411
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Crest factor reduction algorithms described herein may be used to improve power amplifier efficiency during low signal power conditions compared to traditional static threshold techniques. Techniques described herein insure that the signal power level at the output of the crest fact reduction block is held constant relative to the input power level under all signal power level conditions. Two different solutions may be implemented together or separately to achieve the desired conditions. The first technique provides constant ratio between input power and output power. Constant ratio of peak and average output levels keeps the amount of crest factor reduction applied to the signal constant, irrespective of the signal power level. A second technique is to hold signal power level constant in respect to the amount of crest factor reduction applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.