Signal edge detection circuitry and methods
US8416903B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2011 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Apr 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-phased, candidate clock signals are used one after another in order of increasing phase to clock the DDR circuitry. Adjacent bits in the training data that should be equal-valued are captured by the DDR circuitry and compared. Any candidate clock signal that causes the bits thus compared to be unequal is flagged as having phase close to edges in the data. The approximate phase of data edges is thereby indicated by the phase (or phases) of the candidate clock signal (or signals) causing the bits compared as described above to be unequal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.