Circuits, architectures, apparatuses, systems, algorithms, methods and software for on-chip gain calibration
US8417202B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2010 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Mar 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/14
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Circuits, architectures, a system and methods for providing on-chip gain calibration. The circuit generally includes a receiver comprising (i) a resistor on a semiconductor substrate, the resistor configured to provide a signal having a noise component that varies with temperature, and (ii) an amplifier circuit on the semiconductor substrate coupled to the resistor, the amplifier circuit configured to receive the signal and provide a second signal having an amplitude greater than the first signal. The architectures and/or systems generally include those that embody one or more of the inventive concepts disclosed herein. The method generally includes (i) providing a noise signal from a resistor to an amplifier, the resistor being on a common semiconductor substrate with the amplifier, (ii) determining a resistance value of the resistor, (iii) determining an impedance at an input of the amplifier, and (iv) determining a gain of the amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.