Offset cancellation in equalizer circuitry
US8417752B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2009 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Nov 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An equalizer circuitry that includes an equalizer stage having a programmable current source is described. In one implementation, the programmable current source cancels voltage offset. Also, in one implementation, the programmable current source is programmable in user mode. Furthermore, in one implementation, the equalizer circuitry includes a plurality of equalizer stages including the equalizer stage having a programmable current source, where the equalizer stage having a programmable current source is a second equalizer stage in the plurality of equalizer stages. Also, in one implementation, the programmable current source includes a plurality of current sources coupled in parallel and a plurality of sets of control switches for controlling the plurality of current sources. Further, in one implementation, each current source of the plurality of current sources includes a transistor and each set of control switches of the plurality of sets of control switches is for controlling a respective current source and includes a pair of transistors for controlling the respective current source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.