Direct decimal number tripling in binary coded adders
US8417761B2 · kind B2 · utility
1Cited by
15References
20Claims
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Key dates
| Filing date | Dec 8, 2008 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Feb 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4915
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The digital propagate, digit generate, sum+0, and sum+1 terms used in typical carry-propagate adders are generated directly off the multiplicand. During the direct generation, the logic takes into account that each digit will be tripled and if each digit's next less significant digit is greater than 4. Using this technique, the generation of the multiplicand is significantly faster and uses less circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.