System and method of increasing addressable memory space on a memory board
US8417870B2 · kind B2 · utility
99Cited by
159References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 16, 2009 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Feb 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.