Random read and read/write block accessible memory
US8417873B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2009 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Jul 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.