Memory mapping techniques
US8417893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2008 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Mar 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.