Method of fabricating thin film transistor
US8420513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2012 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Mar 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1213
Abstract
A thin film transistor (TFT), including a crystalline semiconductor pattern on a substrate, a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein, a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes, an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein, and source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.