Memory device, memory module and electronic device
US8421081B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2011 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Dec 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.