Non-volatile memory device and method of fabricating the same

US8421141B2 · kind B2 · utility

Assignee

• Powerchip Technology Corporation · TW

Inventors

• Cheng-Yuan Hsu · Hsinchu, TW
• Chun-Hsiao Li · Hengshan, TW

Key dates

• Filing date: Jul 4, 2011
• Grant date: Apr 16, 2013
• Expiry date: Jul 4, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/30

Abstract

A non-volatile memory device includes a substrate, a gate stack, a selecting gate, an erasing gate, a source region, and a drain region. The gate stack on the substrate includes from bottom to top a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a spacer that is located between sidewalls of the control gate and the inter-gate dielectric layer. A side of the floating gate adjacent to the erasing gate has a warp-around profile and a sharp corner protruding from a vertical surface of the spacer. The selecting and erasing gates are respectively located at first and second sides of the substrate of the gate stack. The source region is located in the substrate under the erasing gate. The drain region is located in the substrate at a side of the selecting gate.