Semiconductor device and fabrication method
US8421161B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2010 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Apr 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0156
Abstract
A semiconductor device has a semiconductor substrate in which first and second wells are formed. The substrate and wells are of the same conductivity type, but the second well has a higher impurity concentration than the first well. High-voltage MOS transistors are formed in the first well, and a low-voltage MOS transistor is formed in the second well. The high-voltage MOS transistors include a first transistor having a gate oxide layer with a first thickness and a second transistor having a gate oxide layer with a second thickness less than the first thickness. The low-voltage MOS transistor has a third gate oxide layer with a third thickness less than the first thickness. The second high-voltage MOS transistor provides efficient current conduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.