Wafer level packaged integrated circuit
US8421175B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2009 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Nov 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15788
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level packaged integrated circuit includes an array of contacts, a silicon layer and a glass layer. The silicon and glass layers are bonded together to form a bonding material layer therebetween. The bonding material layer includes gaps between the silicon layer and the glass layer at areas where no bonding material is present. An array of contacts is adjacent the semiconductor layer on a side thereof opposite the bonding layer. The wafer level packaged integrated circuit is provided with additional bonding material layer portions within the gaps and aligned with at least some of the contacts. When the wafer level packaged integrated circuit is configured as an image sensor or display having a pixel array, the additional bonding material layer portions are not used in an area of the pixel array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.