Power reducing logic and non-destructive latch circuits and applications
US8421502B2 · kind B2 · utility
0Cited by
12References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2005 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Nov 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.