Integrated circuit for SRAM standby power reduction in LCD driver
US8421790B2 · kind B2 · utility
0Cited by
9References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2011 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Jan 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0842
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an integrated circuit (IC) for SRAM (Static Random Access Memory) standby power reduction in LCD (Liquid Crystal Display) driver. The IC layout mainly disposes a high-current endurable transistor between a power supply pad and a power supply metal layer of the SRAM matrix. When the IC enters a standby mode, the electrical interconnection between the power supply pad and the power supply metal layer of the SRAM is cut off through the transistor so that the leakage current and the power consumption of the SRAM can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.