Memory controller and memory controlling method
US8422330B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Oct 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register, wherein the data element stored in the register is processed in the storing order by a vector processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.