Packet communication device, packet communication system, packet communication module, data processor, and data transfer system
US8423661B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 1, 2010 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Jan 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3018
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.