Address space emulation
US8423682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Dec 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.