Memory management among levels of cache in a memory hierarchy
US8423715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2008 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | May 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory hierarchy in a computer includes levels of cache. The computer also includes a processor operatively coupled through two or more levels of cache to a main random access memory. Caches closer to the processor in the hierarchy are characterized as higher in the hierarchy. Memory management among the levels of cache includes identifying a line in a first cache that is preferably retained in the first cache, where the first cache is backed up by at least one cache lower in the memory hierarchy and the lower cache implements an LRU-type cache line replacement policy. Memory management also includes updating LRU information for the lower cache to indicate that the line has been recently accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.