Multi-core processing cache image management
US8423717B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Apr 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.