Communications architecture for providing data communication, synchronization and fault detection between isolated modules
US8423823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2011 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Dec 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4256
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic system includes a master module having a first control unit having one or more first serial interfaces and being programmed to output a first data signal and a first clock signal through the one or more first serial interfaces, and a slave module having a second control unit, the second control unit having a second serial interface. The slave module receives the first clock signal through the second serial interface, and the second control unit is programmed to monitor the slave module for a fault condition and output a second clock signal through the second serial interface which is (i) the same as the first clock signal if a fault condition on the slave module is not detected, and (ii) a modified clock signal having a predetermined format through the second serial interface if a fault condition on the slave module is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.