Debug method for computer system
US8423830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2010 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Oct 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A debug method for computer system is disclosed. The method includes the following steps. Firstly, a first index is increased. Next, a first debug data to a jth debug data are received via a debug port of controller. Then, the first debug data to the jth debug data are sequentially stored to a first memory block of a storage unit of the controller according to the second index of controller. Afterwards, the (i+1)th debug data to the jth debug data are copied to the second memory block from the first memory block according to the increased first index before a controller's power supply is removed or the computer system enters a sleep state. Lastly, an application is implemented so that the second memory block is read according to the first index; wherein, i and j are integers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.