Patent · US Active

Method and system for detecting a failure in an error correcting unit

US8423836B2 · kind B2 · utility

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4References
8Claims
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Key dates

Filing dateMay 3, 2010
Grant dateApr 16, 2013
Priority date
Expiry dateOct 30, 2030

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F11/2215
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

In order to detect a faulty error correcting unit (2) in an embedded system, wherein the error correcting unit (2) receives output data from a data source (20) and determines, whether the received data are incorrect, and wherein if the received data are incorrect, the error correcting unit (2) is expected to correct at least one error within the received data, output the corrected data and manipulate an error vector (4), a method and a system (Ia) are suggested that enable to compare the output data of the error correcting unit (2) with at least one reference data, wherein the at least one reference data originate at least indirectly from the data source (20). Both, the error vector (4) and the result of the comparison are input to a plausibility test in order to decide, whether the error correcting unit (2) is faulty. According to the result of the plausibility test, a failure vector (7) is manipulated in order to indicate whether a failure in the error correcting unit (2) is detected.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.