High reliability and low power redundancy for memory
US8423837B2 · kind B2 · utility
3Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2010 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Oct 31, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.