Memory controller and memory system including the same having interface controllers generating parity bits
US8423878B2 · kind B2 · utility
0Cited by
4References
14Claims
0Family size
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Key dates
| Filing date | Apr 12, 2010 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | May 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6306
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.