Methods of manufacturing a vertical type semiconductor device
US8426304B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Nov 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.