Nonvolatile memory devices including multiple charge trapping layers

US8426907B2 · kind B2 · utility

Assignee

• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Kwangmin Park · Seoul, KR
• Juwan Lim · Seoul, KR
• Seungjae Baik · Hwaseong-si, KR
• Siyoung Choi · Seongnam-si, KR
• Kihyun Hwang · Seongnam-si, KR
• Juyul Lee · Daejeon, KR

Key dates

• Filing date: Nov 4, 2009
• Grant date: Apr 23, 2013
• Expiry date: Oct 15, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the substrate and the gate electrode; a charge tunneling layer between the charge trapping layer and the substrate; and a charge blocking layer between the gate electrode and the charge trapping layer. The charge trapping layer includes a first charge trapping layer having a first energy band gap and a second charge trapping layer having a second energy band gap that is different than the first energy band gap. The first and second charge trapping layers are repeatedly stacked and the first and second energy band gaps are smaller than energy band gaps of the charge tunneling layer and the charge blocking layer.