Semiconductor package and method of manufacturing the same
US8426959B2 · kind B2 · utility
4Cited by
13References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2010 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Dec 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.