Logic system with resistance to side-channel attack by exhibiting a closed clock-data eye diagram
US8427194B2 · kind B2 · utility
Inventors
Key dates
| Filing date | May 24, 2011 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | May 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/755
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improvement in the security of a logic system by minimizing observable features such as the power supply or electromagnetic radiation, so called, “side-channel attacks”. Specifically, the present invention comprises a technique and methods for reducing the ability of an intruder to monitor the relationship between currents in the system and the data in the system through the use of a randomized clock wherein the clock eye diagram is closed and without significant reduction in maximum operating speed compared to the reduction in maximum operating frequency that occurs when using conventional means of additive jitter. A system where the clock eye diagram is completely closed is provably more secure than systems where the clock eye diagram is partially open.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.