Patent · US Active

Reduced quantization error I/O resistor calibrator

US8427198B1 · kind B1 · utility

2Cited by

2References

22Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Sridhar Cheruku · Bengaluru, IN
Sivaramakrishnan Subramanian · Savanuru, IN
Nidhir Kumar · Bengaluru, IN

Key dates

Filing date	Dec 16, 2011
Grant date	Apr 23, 2013
Priority date	—
Expiry date	Dec 16, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH04L25/0278
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

Calibration circuitry 42 for an off-chip driver circuit 4 and/or an on-die termination circuit 8 is provided using a parallel network of main transistors controlled by a N-bit calibration value. During the calibration operation, the N-bit calibration value is varied until a threshold impedance value is crossed by the combination of the main transistors. A rounding transistor 52 is then used to determine which of the N-bit calibration values produces a combined impedance closest to the designed threshold impedance.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.