Method and apparatus for fast frequency locking in a closed loop based frequency synthesizer
US8427205B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Dec 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.