Buffer and display device
US8427206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2008 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Aug 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.