Sampling phase lock loop (PLL) with low power clock buffer
US8427209B2 · kind B2 · utility
3Cited by
3References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2012 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Oct 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.