Device for controlling a power transistor
US8427226B2 · kind B2 · utility
2Cited by
2References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 18, 2010 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Feb 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/08122
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to a gate control device for a JFET-type transistor that has a gate, a drain and a source. The gate control device includes a voltage generation circuit comprising an output connected to the gate of the transistor, where the circuit is designed to generate at the output a reference gate-source voltage following a predetermined voltage ramp. A voltage limiting circuit is designed to limit the reference gate-source voltage to a predetermined maximum value when the gate-source voltage at the terminals of the JFET transistor has reached said maximum value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.