System and method for testing power transistors
US8427331B2 · kind B2 · utility
1Cited by
11References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2009 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Feb 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/42
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing a power converter having at least one power transistor is disclosed. The method may include receiving a power transistor test request, and resetting a fault flag. The method may also include applying a gate driver signal to each power transistor, receiving a feedback signal from each power transistor, and determining a difference between the gate driver signal and the feedback signal associated with a respective power transistor. The method may further include identifying a fault if the difference exceeds a threshold profile, and setting a fault flag when a fault is identified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.