Patent · US Active

Time-interleaved pipelined-SAR analog to digital converter with low power consumption

US8427355B2 · kind B2 · utility

6Cited by

5References

5Claims

0Family size

Assignee

University of Macau · CN

Inventors

Sai-Weng Sin · Macau, CN
Li Ding · Hubei, CN
Yan ZHU · Nanhu, CN
He-Gong Wei · Macau, CN
Chi-Hang Chan · Macau, CN
U-Fat Chio · Macau, CN
Seng-Pan U · Macau, CN
Rui Paulo da Silva Martins · Macau, CN
Franco Maloberti · Pavia, IT

Key dates

Filing date	Sep 14, 2011
Grant date	Apr 23, 2013
Priority date	—
Expiry date	Oct 15, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03M1/468
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.