System for address-event-representation network simulation
US8429107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2009 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Aug 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/521
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.