Method of forcing 1's and inverting sum in an adder without incurring timing delay
US8429213B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2009 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Feb 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force_1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force_1 signal. The two functions are implemented without introducing additional delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.