Stashing system and method for the prevention of cache thrashing
US8429315B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2011 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Oct 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a system-on-chip (SoC) including a processor, a method is provided for stashing packet information that prevents cache thrashing. In operation, an Ethernet subsystem accepts a plurality of packets and sends the packets to an external memory for storage. A packet descriptor is derived for each accepted packet and is added to an ingress queue. Packet descriptors are transferred from the ingress queue to an egress queue supplying the packet descriptors to a processor. A context manager monitors the fill level of packet descriptors in the egress queue. In response to monitoring the fill level, the context manager stashes packets from the external memory into a cache, where each stashed packet is associated with a packet descriptor in the egress queue. Packet descriptors are transferred from the ingress queue to the egress queue in response to a number of packet descriptors in the egress queue falling below the fill level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.