Distributed home-node hub
US8429353B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2008 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Jun 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for processor nodes configurable to operate in various distributed shared memory topologies. The processor node may be coupled to a first local memory. The first processor node may include a first local arbiter, which may be configured to perform one or more of a memory node decode or a coherency check on the first local memory. The processor node may also include a switch coupled to the first local arbiter for enabling and/or disabling the first local arbiter. Thus one or more processor nodes may be coupled together in various distributed shared memory configurations, depending on the configuration of their respective switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.