Interleaved hardware multithreading processor architecture
US8429384B2 · kind B2 · utility
1Cited by
21References
31Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 15, 2006 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Feb 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for a digital signal processor alleviates the difficulties and complexities normally associated with writing and optimizing programs to avoid stalls during which one instruction awaits the result of a prior instruction. The architecture coordinates the processing of data for multiple instructions through a multiple stage data pipeline. As a result, the architecture not only supports simultaneous execution of multiple programs, but also permits each program to execute without delays caused by inter-relationships between instructions within the program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.