Edge-based decoders for low-density parity-check codes
US8429483B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2008 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Sep 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6516
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatus are provided for increasing decoding throughput in an LDPC decoder, such as in a wireless communications receiver or in a data retrieval unit. A checker-board parity check matrix and edge-based LDPC decoder structure are provided in which both vertical and horizontal processors are used simultaneously. Horizontal processors may be grouped into type-A and type-B horizontal processors, and similarly, vertical processors may be grouped into type-A and type-B vertical processors. Type-A processors may be used in different clock cycles than type-B processors to update memory locations in a decoding matrix without causing memory access conflicts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.