Error correcting code predication system and method
US8429492B2 · kind B2 · utility
87Cited by
11References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2008 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Feb 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In memory devices that degrade with use, a memory controller may monitor and record a usage history of portions of the memory. The memory controller can then vary a strength of error correction coding to protect information written to various portions of the memory having different usage histories. More specifically, and memory can receive information to be stored in the memory, select a portion of memory to store the information, and store the information in the selected portion of the memory with an error correction coding having a strength that is based on a usage history of the selected portion of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.