Memory storage device, memory controller thereof, and method thereof for generating log likelihood ratio
US8429501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2010 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Dec 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.