Method for preparing for and formally verifying a modified integrated circuit design
US8429580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2011 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Aug 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.