Basic cell architecture for structured ASICs
US8429586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2012 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Mar 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.